Koval'ov Y. Designing of finite state machine models for testbench generation in Active-HDL

Українська версія

Thesis for the degree of Candidate of Sciences (CSc)

State registration number

0401U001492

Thesis Registration Form

0401U001492.pdf

Applicant for

Specialization

  • 05.13.12 - Системи автоматизації проектувальних робіт

27-03-2001

Specialized Academic Board

Д 64.052.02

Kharkiv National University Of Radio Electronics

Essay

Dissertation is sacred to problems of finite state machine designing, whose behavior is represented in VHDL and Verilog language. Мodels of actionable transition graphs of finite state machine are developed. Mentioned models are oriented to optimizied solution of testbench generation, fault-free behavior testing, verification and simulation problems. Control machine testing strategies, which include 3 algorithms of branches-and-bounds of graph tracing, and modified P-algorithm for obtaining decisions as input are offered.

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