Skvortsova O. Test Generation for sequental functional circuits, that realized in programmable logic

The thesis is devoted to the development structural-functional models of sequential circuits and modernization of test generation methods for decreasing of digital systems verification time during all stages of CAD and implementation to FPGA, CPLD chip. Conceptually and structurally complicated model of primitive automata for trigger structures description in one-frame automata format for modeling their fault-free behavior are modernized; sequential device model for realization structural-functional П-algorithm for adequate cubic covering creation for trigger structures for decreasing of analysis time modernized; model of test generation for digital devices verification based on genetic algorithm method for decreasing of for big sequential circuits time modified; modernization of deterministic test generation method that allows test generation for sequential circuits in one copy of iterative model