Bereghnaya M. Techniques for design of logic systems with built-in self-test scheme

The thesis deals with development of techniques, models and algorithms for design of testable logic systems where self-testing hardware implementations are built in these systems. New methods for organizing of diagnostic experiment based on using the testability relations between functional and structural description of the sequential circuit have been proposed. The functional description is represent by a finite state machine and single state-transition fault model is adopted. New method for removing of the functional and redundant have been proposed. An algorithmic procedure is presented which allows to transform the multiple-output Boolean function into a graph of fundamental essential nodes with convergent fan out. New universal model of the syndrome-signature analyzer has been proposed. The method is simple and systematic and computer programs can be easily developed for its implementation.