Kolesnikov K. Deductive method of fault simulation for test generation of digital systems implemented in program logic device

The work was devoted for development of methods and algorithms of back-traced deductive-parallel fault simulation and determined synthesis of the tests on reconfigurable models, these methods permit to decrease the time of the tests quality estimation for complicated digital systems verification at stages of their computer designing no less then 10 times. Process model of the digital circuit deductive-parallel analysis was created on the basis of an inverse superposition procedure; the deductive methods of digital systems’ structurally functional analysis with the purposes of definition of a converging ramifyings set and reconfiguration of pattern for superposition procedure realization was designed; the new topological method of fault simulation with the using of the digital system tree-like structure was designed.