Sarancha S. Methods and means of functional verification of electronic components in CADs

The thesis is devoted to problems of designing of the module of functional control of electronic components at a stage of automated designing with use of the hardware description languages. Model of a two-level method of test pattern generation offered with the purpose of holding the specified protocols of data exchange with an external medium. For a two-level method the conceptual model, model of the generator of arguments of a bus cycles, method of a synchronization of stochastic sources of test patterns, fault coverage criteria are developed. The offered method is realized as a hardware-software complex in structure: waveform viewer/editor Signal Workshop, control system of automated test pattern generation DigItTest, system drivers MicroPort, word generator and logic analyzer.