Yegorov O. Models and methods of co-verification of digital system on a chip

The dissertation work is devoted to functional verification of the complex digital systems on a chip. In work it is developed structural model and method of co-verification of hardware and soft-ware components of the system on a chip. It is defined that major part of system on chip, that consist of reused hardware and soft-ware blocks, can be seated in the field programmable gate arrays during simulation for achieving acceleration during verification. It is improved architecture of hardware/software co-simulation environment that allows co-verification of software blocks together with low level reused hardware blocks and models of hardware blocks under development. It is stated effectiveness of utilization of the software redundancy of hardware description in form of assertions, that allows to automate verification process, reduce test expenses because of usage of randomly generated test. Major results of the research are implemented as hardware/software co-simulation environment CoVer for functional verification of complex systems on chip.