Syrevych Y. Verification of HDL-Models of Digital Devices

The work is devoted to verification of digital devices (DD) models, represented in hardware description languages (HDL). Automation of test generation in computer-aided DD design decreases verification time and decreases system-on-chip design time. Purpose of the work is in developing method of decreasing amount of test information at verification of models of DD, represented in hardware description languages. Improvement of verification strategy of DD-models that allowed automation of verification and coordination of its stages with CAD systems for electronics; improvement of verification methods, based on test generation with path sensitization in a HDL-model; modification of distinguishing sequences for identification of functional elements that allowed decrease of tests; development of data range representation that allowed decrease of processed values and execution of implicative procedures; and development of graph model that allowed executing propagation and justification were proposed