Borysevych A. Methods for synthesis of tests for synchronous digital circuits based on reconfigurable hardware

In the thesis discusses the methods of synthesis of tests for synchronous digital circuits. We propose methods that use structural decomposition testing, symbolic analysis of frag-ments of the circuit, as well as hardware support for the process of synthesis and simulation test failures. The problem of effec-tive use of hardware acceleration of evolutionary search test sequences is solved. Algebra, that describe the controllability of signals in digital synchronous circuits and an algorithm for evaluating the length of test sequences proposed. Developed new fitness functions for the solution of the evolutionary syn-thesis test methods that have injectivity and unimodal proper-ties, and economically implemented in hardware. A hardware architecture for the synthesis of tests, based on shared hardware implementation of the search algorithm and fault simulation subsystem. Using the proposed methods and algorithms can substantially increase the speed of synthesis of checking tests for synchronous digital circuits