Kytsun H. Methods and tools of the reduced instruction set computer processor efficiency increasing

The dissertation is dedicated to the questions of development of new and improvement of existing methods and tools, that will increase an efficiency of the processors, used in the Reduced Instructions Set Computers. For the first time, it is proposed in the dissertation to use a Program Counter for the data addressing in the register file of the processor, and to manage the change of its value by analyzing of the states of the control signals from the cache memory, and of the states of the register file of processor. It is also proposed to employ into the computer memory hierarchy a zero-level instruction cache memory, which will be addressed at the same address space as the register file of processor. New instructions formats for a 32-bit processor are developed and, for the first time, the method of several operands storage under the one address in a register file for polytypic instructions execution is proposed. An efficiency of the proposed improvements has been justified in theory and confirmed at the practice.