Pobezhenko I. System models for designing and verification of JPEG2000 standard wavelet transformation

Research object - develop system models and verification model of JPEG2000 wavelet transformation. Research target is aimed to develop system models and verification model of JPEG2000 wavelet transformation to reduce design time of the digital signal processing components and improve production yield. Research apparatus: personal computer, micro scheme FPGA Xilinx VirtexE-2000. The main results are as follows: verification model for system models of digital signal processing for the JPEG2000 wavelet transformation on the basis of the assertion model; verification and diagnostic maintenance model for program code of DWT SoC; novel logical method for row and column multiplication based on fault detection table to detect single and multiple defects; hardware module of HDL-code automatic generation according to the system model of the wavelet transformation; system model of the arithmetic unit for the JPEG2000 real time wavelet transformation coder with quasioptimal characteristics in the format" DSP transformation quality - SoC hardware complexity"; a model of the arithmetic unit for the JPEG2000 wavelet transformation coder with irrational and flipping coefficients implemented in the functional module of digital system-on-a-chip HES 2000 (VirtexE-2000) with the pipeline architecture of computational processes managed by a specialized hierarchical automation on the basis of counting circuits. It allows three times increasing performance of data compression for DSP transformation.