Yurchenko Y. The method and technique of multi-layer hardware-synchronised majority voting for onboard digital computing systems of space-rocket engineering

The object - functioning of onboard computer systems of critical purpose in severe scheduling of time; the purpose - rise of firmness of the majority redundancy up onboard digital computing systems of severe scheduling of time, fulfilled on single-crystal microcomputers to the failures caused by mistiming of channels, by development and implantation of a method and ways many-tier hardware-synchronised majority voting; methods - methods of synthesis of models of logical units of digital computers for implementation construction on chips FPGA of cells; methods of simulation modelling in the environment of designing FPGA for the logical- timing analysis of phase-frequency characteristics at a transfer function of the synthesised models; probability theory methods - by development of models of an estimation of reliability; novelty - the logical-timing model of majority element for hard time limit On-Board Computing Systems which unlike the known considers various combinations of phases of channels condition and delays of signals distribution in interchannel interfaces is proposed at the first time; it allows to reveal critical chains on time and elements, and also to estimate degree admissible channels asynchronism concerning time distribution in hard limit time operational system cycle; method and architecture of multilayer hardware-synchronised majority voting in onboard digital computing systems on the basis of partial and full hardware synchronised majority voting is improved. It allows to raise stability to the failures caused channels asynchronism, and also to raise system speed of On-Board Computing Systems; the model of an estimation of reliability of majority reservation has received the further development regarding the coverage account majority elements of chains of synchronisation and data that allows to raise accuracy of calculation of indicators of non-failure operation; results - are developed engineering techniques, algorithms and tool FPGA - implementations of models of the clocked functioning of processors in OBC channels; sentences for the projects defining features of application of a technique of the logical timing analysis phase-frequency of characteristics of models and transition functions, projected in FPGA a LSI of blocks are formulated at engineering OBC with a demanded metric of reliability; techniques of a choice and combination of structures of hardware and program ways of support of fault tolerance OBC on the basis of theoretical positions, concrete engineering techniques of the analysis, an estimation of support of reliability are improved; branch - rocket production.