Krainyk Y. Research and development of high-efficient partially parallel LDPC-decoders based on FPGA

Object - information decoding using LDPC-codes based on parity check matrices with random significant element placement using partialy parallel decoders. The goal - raising up efficiency of LDPC-decoders construction for irregular LDPC-codes with random significant elements placement. Methods - theory of finite state machines; theory of parallel computation; theory of information transmission; theory of decision making. Were further developed: models for raising up decoder's throughput. Improved: method for construction of partialy parallel LDPC-decoder with minimal sum decoding algorithm; method for recofigurable partialy parallel LDPC-decoder organization; method of parallel computation organization for partialy parallel LDPC-decoder. Scope - systems with error-correcting ability.