Grushko S. Methods to reduce hardware costs for combined finite state machine on programmable logic chips

The thesis is devoted to solving the topical scientific problem of developing the structures and methods for synthesis of the combined finite state machines (CFSM), aimed at reducing equipment costs when implementing the CFSM logical scheme in the basis of programmable logic integrated circuits such as FPGA and CPLD. The structure of the CFSM was developed for implementation in the FPGA, based on the usage of the heterogeneous FPGA structure, methods for synthesizing the CFSM circuit on the FPGA were improved, making it possible to efficiently usage the basis features of the heterogeneous FPGAs to reduce hardware costs in the CFSM logic circuit. Structures and methods for synthesizing CFSM circuit for CPLD have been developed and improved. It is shown that the usage of these structures provides a reduction in hardware costs in the combined FSM logic circuit by an average of 29.6 %. The scientific and practical problem of minimizing hardware costs in the circuit configuration control unit onboard computing system has been solved. Recommendations on the usage of the proposed structures and methods for the element base of various manufacturers have been developed.