Kuznietsov M. Models and methods of an increase in checkability of circuits on FPGA and in trustworthiness of results in digital components of safety-related systems

Українська версія

Thesis for the degree of Candidate of Sciences (CSc)

State registration number


Applicant for


  • 05.13.05 - Комп'ютерні системи та компоненти


Specialized Academic Board

Д 41.052.01

Odessa National Polytechnic University


The dissertation is devoted to the issues of improvement of digital components designed on FPGA with LUT-oriented architecture for safety-related systems. Models and methods for enhancing the checkability of digital component circuits and the trustworthiness of calculated results are proposed based on the multi-version program code of the FPGA projects to prevent the accumulation of hidden faults and their manifestation in normal and emergency mode, respectively. Models for creating program code versions with inverting LUT memory and rearranging its bits have been developed and investigated. The developed models improve the version redundancy of the solutions and allow to choose the versions to increase the checkability of the circuits and the trustworthiness of the results while maintaining the hardware implementation of the project. On the basis of these models, methods for increasing the checkability of circuits and the trustworthiness of the results for the dominant constant memory failure of LUT units, the fault of closing the address inputs of LUT units and the elimination of hidden faults by their detection and masking respectively in the normal and emergency mode were developed.


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