Larchenko B. Models and methods for designing hardware bit-stream online computers of elementary mathematical functions

The PhD thesis is focused on development of models and methods for designing hardware bit-stream online-computers of elementary algebraic functions for the purpose of increasing calculations accuracy and speed of devices by applying a method of forming step functions increments and fast-acting pipeline structures based on finite-state machine, in order to develop a unified approach to their automated synthesis using hardware description languages. Hardware bit-stream online-computers of elementary mathematical functions are widely used in real-time control systems and have a number of advantages, namely, significant simplification of their technical implementation due to the data being represented by bitstreams, implementation of sequential flow processing at the rate of single bits, high noise immunity. Mathematical models of bit-stream online-computers of linear, power, fractional-rational functions and functions of root extraction have been improved by the method of forming increments of ascending step functions with calculation error minimization. Improved mathematical models of bit-stream online computers of irrational functions are represented by the decomposition of elementary mathematical functions computers' mathematical models, which allowed to expand the functionality of reproducible functions computers. Methods of constructing architectural models of hardware bit-stream online-computers were further developed by using high-speed pipeline structures, which allowed to apply a single approach to their automated synthesis using hardware description languages. For the first time, hardware models of bit-stream online computers of elementary mathematical functions based on finite state machines are proposed. The FSM of the computer's arithmetic unit, containing the state diagram of the control automata of Moore's model and ASM of the offered bit-stream computers containing variable computational states of reproducible elementary mathematical functions was developed. HDL-models of machines in the form of an automatic template were developed, modeled and synthesized on the technological platform of FPGA. The performance of the hardware model of the power online computer was confirmed by verifying the behavioral model, and automated synthesis and implementation on the basis of FPGA. The improved model of the online computer allows to minimize hardware costs, which was confirmed by Quine's estimates of the synthesized models.