Litvinova E. Infrastructures for verification and embedded diagnosis of digital systems-on-chips

Object of the research is the testable designing digital real-time systems and their implementation in the programmable logic chips on the basis of HDL-description languages. Goal is development of infrastructures for verification and diagnosis of digital systems based on using the redundancy of assertion engine and boundary scan to significant reduce time-to-market while increasing product yield. Methods: Boolean algebra, set and graph theories, hardware description languages are applied for the description of primitive functions, methods and models of technical diagnosis, simulation, formal verification, theory of digital automata are applied to develop and implement the infrastructures of verification and embedded diagnosis of digital systems-on-chips; computer-aided design tools, simulation and verification facilities - to implement the proposed models and methods for the Infrastructure IP of digital systems. Theoretical and practical results are the theoretical propositions and practical facilities, which are verification and embedded diagnosis infrastructure for digital systems-on-chips based on assertion engine and boundary scan technology are proposed. Scientific novelty: 1) novel assertion method for SoC HDL-code verification and diagnosis; 2) novel embedded diagnosis method for SoC hardware components; 3) novel testability assessment method for system HDL-code and RTL-models of digital system-on-chip; 4) improved infrastructure for verification and diagnosis of SoC system HDL-models; 5) improved infrastructure for embedded diagnosis and repairing digital systems-on-chips; 6) improved infrastructure for the designing, verification and diagnosing digital systems-on-chips. The author's scientific and practical results are introduced in the following organizations in the form of hardware and software applications and user's guides: Kharkov National University of Radio Electronics; Research Institute of Radio Metering - NIIRI, Kharkov; Close Corporation "Impulse", Severodonetsk; Company Aldec, USA. Scientific and practical results can be used in scientific and technological designing of digital systems-on-chips FPGA (Xilinx) to significantly reduce the time of HDL-model verification and SoC hardware component testing by the developing an infrastructure for design analyzing that allows evaluating the testability of software and hardware modules by constructing a transaction graph in order to use assertion engine and IEEE Std 1500 SECT, which increase the efficiency of simulating, diagnosing and repairing tools.