Sеrgiyenko A. Models, mеthods, and tools for the computer system synthesis intended for data flow computations

A set of methods for pipelined computer systems is developed. The methods are based on mapping the spatial synchronous dataflow graph (SDF) into the computer structure, and its schedule. Methods provide minimizing clock period, hardware volume, register number, multiplexor complexity, energy consumption by the fixed calculation period L. The methods for the pipelined datapath synthesis are developed, which are intended for FPGA, and widely use VHDL as the working language. The methods for mapping Boolean SDF, for buffer synthesis, for hierarchical SDF mapping are proposed as well. The methods are proven by the design of a set of IP core modules for DSP and linear algebra problem solving, which are configured in FPGA. The module parameters s are equal or higher than ones for the best analogous modules. Me-thods of the software pipelining and SIMD system programming are proposed too.