Denysenko Y. Development of theory and methodology of VLSI logical synthesis on the basis of multilevel automata models

Українська версія

Thesis for the degree of Doctor of Science (DSc)

State registration number

0599U000074

Thesis Registration Form

0599U000074.pdf

Applicant for

Specialization

  • 05.13.05 - Комп'ютерні системи та компоненти

15-04-1999

Specialized Academic Board

Д 26.194.03

V.M. Glushkov Institute of Cybernetics of National Academy of Sciences of Ukraine

Essay

The thesis deals with the methodology of VLSI logic design as an open system of interrelated principles, methods and algorithms controlled by mathematical "mechanisms" or author's recommendations. This methodology enables obtaining, within the framework of all logical constraints, (using the example of an LCA-type PLIC) a guaranteed reliable logical circuit adequate to initial data which provides the maximum speed with the minimum expenditure of logical primitives and a predetermining positive solution of topology problems

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