The work solves the scientific and practical problem of reducing the algorithmic complexity of test synthesis and assessing its quality by using the redundancy of smart data structures. The use of read-write transactions on smart data structures in memory instead of a powerful system of processor commands allows you to eliminate iterations of the data bus between the processor and the memory of the von Neumann machine, which leads to saving time and energy when solving the problems of SoC digital components design and test.
The goal of the research is to reduce time costs and increase the adequacy of simulation of test sets and faults, as addresses, through the exponential redundancy of smart data structures based on a logical vector.
Objectives of the study:
1. Development of smart data structures based on a logical vector for solving tasks of technical diagnostics of digital devices.
2. Development of a vector method for the synthesis of a deductive matrix of logical functionality.
3. Development of a vector method for the synthesis of a testing map of logical functionality.
4. Development of a vector method for faults as addresses simulation to evaluate the quality of digital circuit test sets.
5. Software implementation and verification of smart data structures and vector methods for simulation of test sets and faults as addresses.
The object of research is in-memory computing of big data for solving the problems of SoC design and test.
The subject of research is in-memory simulation of tests and faults as addresses for verification of digital logic and circuits.
Equations of technical diagnostics are used to solve tasks of digital product verification. Smart and explicit data structures in the form of logical vector, truth table and activity matrix are built to solve the problems of digital project analysis. The technology of vector simulation of digital circuits is implemented. Methods for generating recoding and activity matrices are being developed to accelerate the simulation of faults as addresses. A logic functionality fault test map is generated based on the recoding and activity matrices. A technology for simulating faults as addresses for analyzing digital circuits is being developed. All these items are aimed at processor-free implementation in memory using read-write transactions on smart big data structures and are focused on saving time and energy during the verification of digital projects.
Scientific novelty of research results:
1. For the first time, a smart data structure is proposed, which is characterized by the parallelism of simulation of test sets and faults as addresses, which enables efficient processing fault vectors of a digital circuit and/or logic element.
2. Vector methods for generating a deductive matrix (verification genome) is improved, which differs from analogues by the use of a recoding matrix and xor operations between a logical vector and test set.
3. For the first time, a vector method for the synthesis of a test map is proposed, which is characterized by the use of a logical vector of functionality and a recoding matrix, which makes it possible solving the problems of test synthesis and fault simulation with a quadratic computational complexity of the algorithm.
4. For the first time, a vector method for fault simulation is proposed, which is characterized by the parallelism of the analysis of faults, as addresses, in the analysis of the logic circuit, which allows to significantly reduce the complexity of the simulation algorithm to a quadratic estimate.
The practical significance of the research results is determined by the following:
Verification of smart data structures and simulation algorithms was performed on dozens of circuits and functional elements from the ISCAS library. The proposed models and methods have been tested at dozens of conferences in the field of EDA, where they received high marks from the leading scientists of the planet for the evidence base, originality, and practical focus of the methods on the electronic technology market. Models, methods, and algorithms are implemented in the Python language, they have been verified on dozens of examples of combinational circuits and complex logical functions. The constraints of the presented mechanisms of fault simulation and test synthesis are related to the dimension of the logical vector, which requires a large value of visual verification of modeling and simulation procedures.
