Hassan K. Models and methods hardware fault simulation for digital systems on chip

Thesis goal - essential (х10, х100) reduction of test quality analysis time by means of application of hardware models and deductive-parallel fault simulation methods based on development of multiprocessor structure with restricted command system. Main results: patterns, methods and algorithms of soft hard-ware deductively parallel fault simulation and Boolean func-tions minimization; structure and functionals of sequensor for solution of deductively parallel fault simulation tasks of complicated digital systems; multiprocessor test quality analysis system that enables to increase speed of fault simu-lation method greatly by means of parallelization and partial piping of primitive processing of design digital device; struc-ture and command system of compiler for allocation primi-tives of digital device described in HDL-language on multi-processor sequensors. The practical importance of received results lies in soft hardware realization of deductively parallel analysis based on use of multi-processorthat is effective solution of verification time reduction problem and essential reduction of time-to-market.