Wade G. Models and methods hardware simulation for digital systems on chip

Thesis goal - essential (x10, x100, x1000) increase of synchronous simulation speed and time verification of computer systems on chips by means of use multivalued hardware models of components, which enable to enlarge functionality of logical hardware analysis facilities for identification of transient processes and determination of competitions at early design stages of digital devices.Main results: testing and verification models of digital projects, which are oriented on hardware implementation for essential (х10, х100, х1000) reduction of simulation time; hardware realization of the ternary fault-free behavior simulation method HES-MV - Hardware Embedded Simulation based on Multi-Valued alphabet that uses hardware patterns of large dimension digital projects gate and register description level; structural solutions for realization gating circuit patterns, which have two bits for coding of four states of every input or output line of simulated device; hardware models of digital devices and primitives, which enable to enlarge functionality of hardware simulation method for analysis of transient processes and to increase speed of software simulation essentially at project verification.The practical importance of application of hardware simulation technology lies in that there appear possibility to reduce time-to-market of complete product essentially (by 15-30%).