Guz O. Structure-functional testability analysis at design of digital system-on-chip

Thesis goal – development of models and methods of the structural-functional testability analysis of design digital system-on-a-chip, which enable to reduce the verification time and to decrease the diagnostic information volume at simultaneous improvement of the test quality and fault diagnostic depth. Main results: new structure-functional SoC testability analysis method (TADATPG), new functional strongly connected three-component TFY-model of SoC testing, new noniterative model of SoC diagnostic, improved model of test point choice process, improved P-algorithm of cubic covering synthesis. Practical importance of gained results consists of software implementation the models and method of testability analysis and choice of SoC critical scan point for test synthesis, fault simulation and diagnostic; implementation of testability analysis and SoC modification software to the system SIGETEST, valid testing of the method, models and software by means of their compare with foreign analogs using testlibraries of the leading firms, as well as their integration to modern design routes on basis of boundary scan standards IEEE (11.49, 1500).