Kaminska M. System's models of testability analysis of digital structures on chips

The thesis is devoted to development of models and methods of the structural-functional testability analysis of design digital system-on-a-chip, represented by gate level, RT level and system level and software products, represented as sys-tem level and described on algorithmic description languages for essential reduction of the verification time due to of its modification and application of the boundary scan tech-nology for digital circuits and assertions for software prod-ucts, which enable to decrease the diagnostic information volume at simultaneous improvement of the test quality and fault diagnostic depth. New structure-functional SoC testability analysis method is offered for the first time; new testability analysis methods for software, functional blocks of them are represented as composition of control and operational automata (TASL and TGA), new noniterative model of SoC diagnostic, improved model of test point choice process, testing procedure realization based on weighted test generation based on testability analysis method, new technological model of assertions usage, based on testability analysis.