Ngene C. Embedded diagnostic infrastructure for HDL models of digital systems-on-chips

The goal is to reduce HDL-code verification time and improve the quality of ESL-models for digital systems-on-chips by using software-hardware redundancy in the design technology, which provides the desired diagnostic resolution of the HDL-code. Main results: a new analytical process model for testing and verification, which is characterized by the use of beta-metric that makes it possible to formulate all existing problems of technical diagnostics of software and hardware components of digital systems-on-chips; a new structural model of HDL-code in the form of transaction graph, which makes it possible to search for functional violations during code simulation; based on the assertion engine a group of improved methods for diagnosing functional violations in HDL-code was developed, which significantly reduce the analysis time of simulation results when searching for faults; improved architecture of logic associative multi-matrix processor with limited instruction set, which is focused on embedded Infrastructure IP for functional blocks of digital systems-on-chips. The proposed models and methods for testing, as well as the dedicated multi-matrix processor were implemented in the form of hardware-software infrastructure components and integrated into Riviera (Aldec) simulation environment. This allows for the creation of an efficient infrastructure for verification and diagnosis of HDL-code of digital systems-on-chips. The practical significance of the results: 1. Models and methods for testing, as well as dedicated architecture of the multimatrix processor are realized in the form of hardware-software infrastructure components, integrated with the system of Riviera (Aldec), which allowed creating efficient flow-charts for testing and diagnosis of HDL-code for digital systems-on-chips. 2. Integration of software HDL-models and hardware implementation of methods for diagnosing functional failures allowed significantly reducing (20%) the time for simulation and verification when testing digital products. 3. HDL-testing infrastructure provides hardware processing the hardware-software models of designed product that allows significantly (50%) reducing the time for diagnosis and correction of the code when debugging. 4. The proposed models and methods, which are the basics of software-hardware testing infrastructure based on assertion engine, significantly (20%) increase the testability of digital systems that allows reducing the time for the test synthesis and increasing its functional completeness and quality of the designed product.