Tiecoura Y. Vector-logic infrastructure for embedded testing digital systems-on-chips

The aim of the research is to improve the test-infrastructure IP of digital systems-on-chips by the introduction of embedded hardware and software redundancy in the form of the functional component infrastructure that provides the desired diagnosis depth. The subject of the research is the processes of embedded testing digital systems-on-chips, including test synthesis and fault detectiom, based on the standard boundary-scan. Main results: a new model for interacting discrete objects in cyberspace, which is characterized by the use of scalar and vector value of beta metric, which allows accurate and adequately evaluate the solutions, when searching and recognizing any objects in the vector logic space, and in parallel solving the problems of synthesis and analysis of diagnosis information; improved structural model of the digital system, which is distinguished by the transaction graph of functional modules, which is invariant to hierarchy levels of the product and allows simplifying the preparation and presentation of diagnostic information in the form of minimized activation table of functional blocks or destructive components on the test segments; improved methods for test synthesis and fault diagnosis, based on boundary-scan, for functionalities specified by matrix forms describing the behavior of digital components, which differ parallel vector operations on fault detection tables and allow reducing memory volume and repair time of digital system; improved architecture of logic associative multiprocessor, focused to increase the productivity of embedded fault diagnosis, which differs by using parallel vector logical operations and, or, xor, slc, which makes it possible to reduce the diagnosis time for single and multiple faults by activation table of functional modules. Models and methods of Infrastructure IP and architecture of dedicated multiprocessor are implemented in the software and hardware, using the boundary-scan technology. It allows creating efficient flows and process models for test synthesis and diagnosis of functional modules of digital systems-on-chips. The Infrastructure IP can detect a wide range of fault blocks of digital systems-on-chips that allows significantly (30%) reducing the diagnosis time of hardware components in functioning; proposed models and methods are the mathematical basis of the Infrastructure IP and significantly (20%) increase the testability of digital system.