Almadhoun S. Methods of design errors search in HDL-models of digital devices

Object of research is: digital device models, represented in hardware description languages in computer-aided design systems. Research scope is: structural and functional methods for design error search in digital. Research techniques are: Boolean algebra apparatus, automata and graph theory, technical diagnostics and formal verification; computer-aided design tools for digital devices. Equipment is: tool software for computer-aided design of digital systems Active-HDL for OS Windows. Theoretical and practical results of the research are: automation procedure of conducting a diagnostic experiment on design errors search in HDL-models on functional and block level at functional verification. Developed methods of design error search in HDL-models of digital devices and modification of HDL-model verification environment are integrated into computer-aided design system Active-HDL, which helped to reduce time expenses on design error search at functional verification of digital devices models. Scientific novelty is: a method of backtracing for a graph model of an HDL-code was introduced for the first time that made it possible to significantly raise design errors search depth at an incomplete specification of a device to be designed; a graph model of an HDL-code and the design error model were improved that made it possible to extend the detectable design errors class; a structural method of design errors search based on graph-models using a reachability matrix and an experimental validation vector was modified that made it possible to concise precautionary design errors area and reduce time for design errors search in HDL-models; a design errors search method based on fault dictionaries using fault function tables and modified verification environment for HDL-models (TestBench) got further development that made it possible to diminish diagnostic experiment length at design errors search in HDL-code; a method for design errors search in HDL-models of finite state machines which are set as transition graphs got further development that made it possible to locate design errors up to certain conditional operators in HDL-code. The dissertation outcomes are implemented in LLC "Aldec-КТS" at computer-aided design of digital devices using CAD Active-HDL and simulation software Riviera™ by Aldec Inc. (USA), as well as in the classes of Kharkiv National University of Radioelectronics.