Sysenko I. Deductive-Parallel Fault Simulation on Reconfigurable Models of Digital Systems

The thesis is devoted to the development of the fast stuck-at-fault simulation methods on the reconfigurable models of digital systems, oriented on its implementation in programmable logic with purpose of synthesized test quality evaluation. The model of deductive-parallel fault analysis, combines deductive fault simulation processibility and processing speed of parallel vector was modified; deductive model of data structure reconfiguration, which allows processing of the set of faults in one iteration with purpose of applied input sequences evaluation speed-up was proposed; the deductive-parallel fault simulation method for digital devices, represented on gate level and register transfer level in form of Boolean equations was developed; the backtraced fault simulation method of VLSI circuits with using of deductive-parallel procedures for reconvergent fan-outs evaluation and backtracing for tree-type structures was improved