Kogut I. The microsystem elements based on the gate arrays chip on the silicon-on-insulator structures.

Українська версія

Thesis for the degree of Doctor of Science (DSc)

State registration number

0510U000311

Thesis Registration Form

0510U000311.pdf

Applicant for

Specialization

  • 05.27.01 - Твердотільна електроніка

26-03-2010

Specialized Academic Board

Д 35.052.12

Lviv Polytechnic National University

Essay

The new technological methods formation of the local planar and tree dimensional SOI-structures are development. These structures are good as well as for IC elements and for microsystem-on-chip sensitive elements design, include three dimensional architectures with monolithic integration on the specialized, for mycrosystem applications, SOI CMOS gate arrays chip. Posibilities of using the device SOI-structures for hard enviropments are investigated. Some new three dimensional SOI-elements for microsystem-on-chip are developed.

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